1. Field of the Invention
The present invention generally relates to a method of manufacturing a semiconductor device. More particularly, the present invention generally relate to a method of forming a trench in a semiconductor device.
A claim of priority is made to Korean Patent Application No. 2004-39224, filed on May 31, 2004, the disclosure of which is incorporated by reference.
2. Description of the Related Art
With recent developments in semiconductor devices, the size of components in the semiconductor devices has dramatically decreased. In addition, the integration of the semiconductor devices has rapidly increased. A reduction in chip size is regarded as an important factor in the development of highly-integrated semiconductor memory devices.
Many efforts have been made to reduce the chip size for a dynamic random access memory (DRAM) device. As a result of these efforts, a cell structure has changed to a planar alignment or a layout of active regions. A conventional layout for active regions is an 8F2 type structure. By changing an alignment of the active regions in such a structure, research is being done to further reduce a unit cell size while still using a minimum line width F in the 8F2 type structure.
As the integration of the semiconductor devices increases, coupled with the reduction in design rule, it has become more difficult to guarantee stable transistor operation. Further, as a width of a gate is reduced, short channel problems increases.
The short channel also produces punch-through between source and drain regions of the transistor. The punch-through is the main cause of transistor malfunctions. Therefore, many methods have been used to ensure a minimum channel length in order to overcome short channel problems. Specifically, attempts have been made to increase the channel length by recessing a semiconductor substrate under a gate in order to expand the channel length relative to a gate line width. There are many conventional methods of forming a MOS transistor having a recessed channel.